Bit Error Rate Monitoring

Today's telecommunications needs call for faster and more reliable networks. Optical transmission has allowed great advances in creating faster and more reliable global communications networks. Most optical networks are based on the SONET (North American) and SDH (International) standards. For my thesis, I have designed, implemented, and tested a bit-error rate monitoring circuit, compliant with both SONET and SDH standards. This circuit was designed as part of a SONET/SDH Framer, and plays an important role in monitoring the reliability of the optical network. The circuit was designed to be as efficient as possible, taking into account both the gate count and the expected power consumption. The circuit was designed using VHDL, a high-level hardware description language, and Cadence tools were used to compile and synthesize the design. The final bit-error rate monitor circuit consisted of about 40,000 gates, and 5,000 flip-flops, with an estimated power consumption of three quarters of a milliwatt. The power consumption and circuit size were well within the amount allotted for the circuit. The circuit functionality was tested both independently, for faster simulations, and as a part of the overall SONET/SDH Framer. Functional simulations verified circuit functionality before fabrication, thus, reducing costs associated with multiple circuit revisions. Overall, this thesis project has helped me gain a better understanding of the overall circuit design, test, and implementation process. I have gained invaluable knowledge and experience that I can apply as a Circuit Designer. iv ACKNOWLEDGMENTS I would like to offer many thanks to Barry Tsuji, Ljiljana Trajkovic and Kevin Citterelle for serving on my thesis committee, as well as Steve Whitmore for editing this document. I would also like to thank everyone at West Bay Semiconductor for their assistance in putting together this thesis. Special thanks go to my wife, Elia Robles, for her support.